1. Field
This invention relates to memory devices. In particular, the invention relates to data strobing.
2. General Background
Double Data Rate (DDR) memory devices use source synchronous transfers when data is read from the memory devices. The data strobe signal (DQS) is sent along with the data (DQ) to be clocked. The clocking edges of the DQS signal are coincidental with the data transition time. To capture the data in a register using the DQS signal, the DQS signal needs to be delayed to satisfy the data set-up time requirement of the register. For 100 MHz DDR devices, the required delay time is approximately 2 nsec.
Delay elements tend to have drift due to heat, aging, and other environmental factors. To adjust the delay amount, the delay elements have to be periodically calibrated. Existing techniques to calibrate the delay elements use a master/slave relationship. A master delay element is used only for calibration while a slave delay element is used only for operation. These techniques have a number of disadvantages. First, the number of delay elements is doubled, requiring more space and area. Second, the master and slave delay elements may have different characteristics due to process variation, temperature sensitivity, and voltage variations.
Therefore, there is a need to have an efficient technique to calibrate the delay elements.